Reconfigurable Hardware Implementation and Analysis of Mesh Routing for the Matrix Step of the Number Field Sieve Factorization

RECONFIGURABLE HARDWARE IMPLEMENTATION AND ANALYSIS OF MESH ROUTING FOR THE MATRIX STEP OF NUMBER FIELD SIEVE FACTORIZATION Sashisu M. Bajracharya, M.S. George Mason University, 2004 Thesis Director: Dr. Kris Gaj Factorization of large numbers has been a constant source of interest as it is the basis of security for the well-known RSA cryptosystem. The fastest known algorithm for factoring large numbers is the Number Field Sieve (NFS). The most time consuming phases of NFS are Sieving and Matrix Step. This thesis is concentrated on the Matrix Step, and an efficient way of implementing this step in reconfigurable hardware is proposed. This solution is based on the Mesh-Routing method, proposed by Lenstra et al., for which only theoretical estimates have been reported. The Mesh-Routing method has been implemented in the FPGA devices in order to come up with the concrete performance measures. The two types of Mesh Routing method, basic and improved, have been implemented and compared. Based on the experimental results for a partial mesh implemented on a single FPGA, the execution times of the Matrix Step for the case of factoring 512-bit and 1024-bit numbers have been calculated. The computation time for the case of a square systolic array of FPGAs interconnected among each other has